Validate a RISC-V Core. Automate the Flow. Prove Compliance.

Introduction

The Pakistan Semiconductor Summit is hosting a hands-on RISC-V Architectural Compliance Hackathon to give students and early-career professionals direct exposure to real-world processor verification workflows.

The hackathon focuses on the official RISC-V Architectural Test Suite, a set of assembly-level, self-checking tests that verify whether a RISC-V implementation complies with the ISA specification. These tests are widely used in both industry and academia for architectural compliance.

Participants will run these tests on either their own RISC-V implementation or an assigned candidate processor, analyze the results, and develop an automated reporting flow. This workflow will illustrate how processor validation and compliance are conducted in professional engineering environments.

Eligibility Criteria

• Designation:
  • Students and early professionals with a degree in Electrical Engineering, Computer Science, or Computer Engineering.
• Recommended skills:
  • Basic understanding of computer architecture and digital system design
  • Programming experience in C/C++, Assembly, Python, etc.
  • Familiarity with compilation and build systems
  • Comfort using the Linux command line
• Deadline for registration – 03/15/2026