10xEngineers is hosting a hands-on FPGA & RTL design hackathon to give students real-world experience in chip design workflows. Participants will be provided with a pre-written RTL design and will use either Cadence EDA tools or open-source FPGA design tools to take that RTL through essential stages of the chip design flow.

Format:

• This is a research-oriented hackathon, hosted 10xEngineers at SDSB LUMS, Lahore
• Each team or individual participant will receive access to the FPGA design environment along with a handbook and resources about benchmarks.
• Teams will perform specific tasks on the RTL design and provide a detailed analysis of their results.

Eligibility / Selection Criteria

• Final year students from Computer Engineering, Computer Science, or Electrical Engineering.
• Good understanding of Linux fundamentals, FPGA/RTL design basics, and strong research skills.

A screening round will be conducted before the final selection of teams.