Compiler-Driven Scalable Vector Optimization for RISC-V: Addressing MLIR's RVV Limitations Using IREE

"One Student One Chip" Mambo Robot: RISC-V Processor Chip Showcase Using Open-Source IP, EDA, and PDK

Custom Hardware Accelerator Integrated with NEORV32 RISC-V Processor

Enhancing Reliability, Availability, and Serviceability in RISC-V Systems through the RAS Error Record Register Interface (RERI)

A Resource-Efficient Fixed-Configuration QC-LDPC Encoder Architecture for 5G NR Physical Layer

FPGA Implementation of Walsh–Hadamard Transform for HEVC Encoders

Breaking the Throughput–Area Trade-off: An Efficient ASCON-128A Hardware Accelerator

Design and Verification of a Single-Master DMA Controller with AHB Interface

Design and Verification of a DDR3 SDRAM Controller with Command and Data Management for Embedded Systems

A Secure-by-Default RISC-V Microcontroller for Zero-Trust IoT Nodes

Middleware API Exposure for GPS & Cellular Modules on Android Platforms

Rate-Distortion Optimized Quantization Design for HEVC (H.265) Encoder

Context-Based Adaptive Binary Arithmetic Coding for HEVC/H.265 Encoder

Design and Verification of a Bosch CAN 2.0A/B Compliant Controller Area Network (CAN) Bus IP Core in SystemVerilog

Implementation of Enhanced Subservient Core with FPU Co-processor and Sensor Integration

Design of an Integrated Modulo Sampling ADC for Passive Radars

Design of a 4-Bit AC Nano-Processor for Self-Powered Biomedical and Smart Dust Applications

Edge AI SoC IP Integration

Custom Edge AI Vision SoC — From Concept to GDSII

RISC-V SoC with Digital In-Memory Compute Based AI Accelerator

HW/SW Co-design based Reconfigurable Accelerator for Inference of LLMs Empowering Real-Time Edge Intelligence

Cross-Platform Optimization of Edge AI Accelerators: A Comparative Study using OpenVINO and Vitis AI

Efficient Multiplier Architectures for CNN-Based Image Processor

RISC-V Co-Processor for Transformer Acceleration