Technical Sessions

Technical Session Schedule

2.00pm – 3.30pm

28th March, 2026

2.00 – 2.15 2.15 – 2.30 2.30 – 2.45 2.45 – 3.00 3.00 – 3.15 3.15 – 3.30

Room B3

2.00 – 2.15

Resistor-Less Current Sensor

Muhammad Bilal

GF-METRC / ICD Lab, NUCES (FAST-NU) Islamabad

2.15 – 2.30

Design and Implementation of an On-Chip Phase-Locked Loop for FM Broadcast Band Application

Zain Jahangir

National University of Computer and Emerging Science

2.30 – 2.45

Low Power, High CMRR Gain-Programmable Instrumentation Amplifier for Skin Impedance Spectroscopic Characterization

Aisha Khan

NUST

2.45 – 3.00

Wideband Operational Amplifier with Integrated Current-Adjusting Auto-Zero Offset Cancellation

Muhammad Anwar Ansari

FAST NUCES, Islamabad

3.00 – 3.15

A Tri-loop Fast-transient Digital LDO with Adaptive-gain Control and Fine-loop Freezer

Saad Munawar

NUST Chip Design Centre (NCDC)

3.15 – 3.30

A High-throughput Impedance Measurement IC with Baseline-Canceling Peak Detector

Abdur Rehman Ejaz

NUST Chip Design Centre (NCDC)

Room B2

2.00 – 2.15

Verimate: A GenAI-Powered Framework for Automated UVM-based Verification Plan and Environment Generation

Syed Saad Akhtar

MERL, UITU

2.15 – 2.30

Mind the Gaps: A Survey of Reusability and Interconnect Challenges in UVM-Based SoC Verification

Malyka Awais

NUST

2.30 – 2.45

Scalable UVM Verification Components (UVCs) to Accelerate Functional Verification of SoCs

Muhammad Yasir Farooq

National Electronics Complex of Pakistan (NECOP)

2.45 – 3.00

Customizable Verification Framework for Mil-Std 1553 Avionics Bus Interface

Muhammad Kashif Minhas

CESAT

3.00 – 3.15

Scaling Formal Verification of Network On Chip Using Path Decomposition

Bilal Ahmed

10xEngineers

3.15 – 3.30

Design and Development of RISC-V Based Virtual Cluster using QEMU Simulator

Tassadaq Hussain

Namal University Mianwali

11.30am – 1.15pm

29th March, 2026

11.30 – 11.45 11.45 – 12.00 12.00 – 12.15 12.15 – 12.30 12.30 – 12.45 12.45 – 1.00 1.00 – 1.15

Room B3

11.30 – 11.45

Vaquita: A Portable Four Stage Pipeline RISC-V Vector Co-Processor

Farhan Ahmed Karim

Micro Electronic Research Lab (MERL)

11.45 – 12.00

Energy Efficient 3D CNN Inference using Multi-dimensional Systolic Architectures on FPGA

Fatima Hameed Khan

LUMS / FAST

12.00 – 12.15

Design of an Image Processing Accelerator for FPGA-based Systems

Haroon Waris

PIEAS

12.15 – 12.30

FOSSSC: A Free, Open-Source Software Stack Cluster for Digital System Design

Tassadaq Hussain

Namal University, Mianwali

12.30 – 12.45

Infinite-ISP: An Open Source Hardware Image Signal Processor Platform for all Imaging Needs

Taimur Bilal

10xEngineers

12.45 – 1.00

ORSGRAND: Hardware-Efficient Ordered Reliability Symbol GRAND Decoder for Low-Latency Multiuser IoT Applications

Arslan Hassan

LUMS

1.00 – 1.15

Design and Spectral Performance Analysis of a 32-bit DDS with 10-bit Segmented Current-Steering DAC

Muhammad Uzair Ishaq

ICD Lab, NUCES (FAST-NU) Islamabad Campus

Room B2

11.30 – 11.45

Metastability and Jitter Based True Random Number Generator for AES

Mohsan Abbas

ICD Lab, NUCES (FAST-NU) Islamabad Campus

11.45 – 12.00

SoC-Now: An Open-Source RISC-V SoC Generation Framework from RTL to Silicon

Talha Ahmed

UIT University

12.00 – 12.15

Camera Imaging Systems for Modern Semiconductor Application

Muhammad Danial

10xEngineers

12.15 – 12.30

Designing Reusable Hardware Library in Chisel

Tariq Bashir

10xEngineers

12.30 – 12.45

UET-RVMCU: A Resource-Efficient RISC-V Microcontroller with Bit Manipulation Extensions for Low-Cost FPGA Deployment

Shehzeen Malik

UET Lahore (MEDS)

12.45 – 1.00

A High-Performance Dual-Core AES-128 Accelerator Implemented in FPGA & 65nm CMOS

Abdul Rehman

University of Engineering & Technology, Taxila

1.00 – 1.15

A Real-Time Brain-Computer Interface with FPGA-Accelerated Neural Signal Processing and Enhanced EEG Classification using Adaptive SVM

Tassadaq Hussain

Namal University Mianwali

Overview The Expert Technical Sessions bring together leading professionals from industry and academia to share in-depth insights across the semiconductor value chain. They focus on applied innovation, design methodologies, manufacturing practices, and emerging technologies shaping the future of semiconductor engineering.Both industrial case studies and research-driven technical contributions are welcome.Topics of Interest we welcome tutorials in (but not limited to):
  • RISC-V Architecture & Extensions
  • RTL Design & Microarchitecture
  • Functional Verification (UVM, Formal, Coverage)
  • Physical Design & Backend Flow
  • EDA Tools & Automation
  • FPGA Prototyping
  • AI Accelerators & Edge AI Hardware
  • Embedded AI
  • Chiplet & Advanced Packaging
  • Semiconductor Testing & DFT
  • Low-Power Design Techniques
  • Analog & Mixed Signal Design
  • Hardware Security
  • Semiconductor Startup Case Studies
  • Talent Development & Semiconductor Education
Format Selected speakers will deliver structured oral presentations within the official technical program. Each session encourages:
  • Deep technical engagement
  • Practical knowledge exchange
  • Industry–academia collaboration
Submission Guidelines
  • Prospective speakers are invited to submit short papers in standard two-column IEEE format.
  • Previously published or presented work may also be submitted.
  • Submission Deadline: February 27th, 2026
Why Participate?
  • Showcase your expertise on a national semiconductor platform
  • Engage with ecosystem leaders
  • Contribute to Pakistan’s semiconductor capability development